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2.1 On Resistance, 15 V/+12 V/5 V iCMOS Dual SPST Switches ADG1421/ADG1422/ADG1423
FEATURES
2.1 on resistance 0.5 maximum on resistance flatness Up to 250 mA continuous current Fully specified at +12 V, 15 V, 5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 10-lead MSOP and 10-lead, 3 mm x 3 mm LFCSP packages
FUNCTIONAL BLOCK DIAGRAM
ADG1421
S1 IN1 D1 D2 IN2 S2
08487-001
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1. ADG1421 Functional Block Diagram
APPLICATIONS
Automatic test equipment Data acquisition systems Relay replacements Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems
ADG1422
S1 IN1 D1 D2 IN2 S2
08487-002 08487-003
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 2. ADG1422 Functional Block Diagram
GENERAL DESCRIPTION
The ADG1421/ADG1422/ADG1423 contain two independent single-pole/single-throw (SPST) switches. The ADG1421 and ADG1422 differ only in that the digital control logic is inverted. The ADG1421 switches are turned on with Logic 1 on the appropriate control input, and Logic 0 is required for the ADG1422. The ADG1423 has one switch with digital control logic similar to that of the ADG1421; the logic is inverted on the other switch. The ADG1423 exhibits break-before-make switching action for use in multiplexer applications. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The iCMOS(R) (industrial CMOS) modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has achieved. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.
ADG1423
S1 IN1 D1 D2 IN2 S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 3. ADG1423 Functional Block Diagram
The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. The iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 2.4 maximum on resistance at 25C. Minimum distortion. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. 10-lead MSOP and 10-lead, 3 mm x 3 mm LFCSP packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADG1421/ADG1422/ADG1423 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 +12 V Single Supply ..................................................................... 4 5 V Dual Supply ......................................................................... 5 Continuous Current per Channel, S or D ..................................6 Absolute Maximum Ratings ............................................................7 Thermal Resistance .......................................................................7 ESD Caution...................................................................................7 Pin Configuration and Function Descriptions..............................8 Typical Performance Characteristics ..............................................9 Test Circuits ..................................................................................... 12 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG1421/ADG1422/ADG1423 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG1423 Only) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) 25C -40C to +85C -40C to +125C VDD to VSS 2.1 2.4 0.02 0.1 0.4 0.5 0.1 0.5 0.1 0.5 0.2 1 2.8 0.12 0.6 3.2 0.13 0.65 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ Test Conditions/Comments
VS = 10 V, IS = -10 mA; see Figure 23 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V; see Figure 24 VS = 10 V, VD = 10 V; see Figure 24 VS = VD = 10 V; see Figure 25
2 2 2
75 75 75 2.0 0.8
0.005 0.1 4 115 145 115 145 45 -5 -64 -74 0.016 180 0.12 18 22 86
VIN = VGND or VDD
180 165
210 190 30
RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 27 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz; see Figure 32 RL = 50 , CL = 5 pF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V
Rev. 0 | Page 3 of 16
ADG1421/ADG1422/ADG1423
Parameter POWER REQUIREMENTS IDD IDD ISS VDD/VSS
1
25C 0.002
-40C to +85C
-40C to +125C
Unit A typ A max A typ A max A typ A max V min/max
Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V, or VDD Ground = 0 V
1.0 120 190 0.002 1.0 4.5/16.5
Guaranteed by design, not subject to production test.
+12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG1433 Only) Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth 25C -40C to +85C -40C to +125C 0 V to VDD 4 4.6 0.03 0.15 1.2 1.5 0.05 0.5 0.05 0.5 0.1 1 5.5 0.17 1.75 6.2 0.18 1.9 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ
Rev. 0 | Page 4 of 16
Test Conditions/Comments
VS = 0 V to 10 V, IS = -10 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA VS = 0V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V; see Figure 25
2 2 2
75 75 75 2.0 0.8
0.005 0.1 4 180 230 130 165 70 30 -60 -70 140
VIN = VGND or VDD
295 205
340 235 48
RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 27 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31
ADG1421/ADG1422/ADG1423
Parameter Insertion Loss CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD IDD VDD
1
25C 0.26 31 36 90 0.001
-40C to +85C
-40C to +125C
Unit dB typ pF typ pF typ pF typ A typ A max A typ A max V min/max
Test Conditions/Comments RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V Ground = 0 V, VSS = 0 V
1.0 120 190 5/16.5
Guaranteed by design, not subject to production test.
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN 25C -40C to +85C -40C to +125C VDD to VSS 4.5 5.2 0.04 0.18 1.3 1.6 0.05 0.5 0.05 0.5 0.1 1 2 2 2 75 75 75 2.0 0.8 0.005 0.1 4 6.2 0.2 1.85 7 0.21 2 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ Test Conditions/Comments
VS = 4.5 V, IS = -10 mA; see Figure 23 VDD = +4.5 V, VSS = -4.5 V VS = 4.5V; IS = -10 mA VS = 4.5 V, IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VS = 4.5 V, VD = 4.5 V; see Figure 24 VS = 4.5 V, VD = 4.5 V; see Figure 24 VS = VD = 4.5 V; see Figure 25
VIN = VGND or VDD
Rev. 0 | Page 5 of 16
ADG1421/ADG1422/ADG1423
Parameter DYNAMIC CHARACTERISTICS 1 tON tOFF Break-Before-Make Time Delay, tD (ADG1433 Only) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C 285 370 220 295 85 82 -60 -70 0.04 150 0.25 25 30 100 0.001
-40C to +85C
-40C to +125C
Unit ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max V min/max
Test Conditions/Comments RL = 300 , CL = 35 pF VS = 3 V; see Figure 26 RL = 300 , CL = 35 pF VS = 3 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = 3 V; see Figure 27 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 k, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 32 RL = 50 , CL = 5 pF; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0V, f = 1 MHz VS = 0V, f = 1 MHz VS = 0V, f = 1 MHz VDD = 5.5 V, VSS = -5.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD Ground = 0 V
460 350
520 395 45
1.0 0.001 1.0 4.5/16.5
Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 4.
Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply 10-Lead MSOP (JA = 142C/W) 10-Lead LFCSP (JA = 76C/W) +12 V Single Supply 10-Lead MSOP (JA = 142C/W) 10-Lead LFCSP (JA = 76C/W) 5 V Dual Supply 10-Lead MSOP (JA = 142C/W) 10-Lead LFCSP (JA = 76C/W)
1
25C
85C
125C
Unit
Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V
185 250 150 205 145 195
120 155 100 130 100 125
75 85 65 80 65 75
mA maximum mA maximum VDD = 10.8 V, VSS = 0 V mA maximum mA maximum VDD = +4.5 V, VSS = -4.5 V mA maximum mA maximum
Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 16
ADG1421/ADG1422/ADG1423 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 5.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs
1
THERMAL RESISTANCE
Table 6. Thermal Resistance
Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Package Type 10-Lead MSOP (4-Layer Board) 10-Lead LFCSP JA 142 76 JC 44 Unit C/W C/W
ESD CAUTION
Peak Current, S or D (Pulsed at 1 ms, 10% Duty-Cycle Maximum) 10-Lead MSOP (4-Layer Board) 10-Lead LFCSP Continuous Current per Channel, S or D Operating Temperature Range Industrial Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free
1
300 mA 400 mA Data in Table 4 + 15% mA
-40C to +125C -65C to +150C 150C 260C
Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 7 of 16
ADG1421/ADG1422/ADG1423 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
S1 1 S2 2 NC 3 GND 4 VDD 5
ADG1421/ ADG1422/ ADG1423
TOP VIEW (Not to Scale)
10 D1 9 8 7 6 D2 VSS IN1 IN2
08487-004
S1 1 S2 2 NC 3 GND 4
10 D1
ADG1421/ ADG1422/ ADG1423
TOP VIEW (Not to Scale)
9 8 7 6
D2 VSS IN1
08487-005
NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT
VDD 5
IN2
NC = NO CONNECT
Figure 4. 10-Lead LFCSP Pin Configuration
Figure 5. 10-Lead MSOP Pin Configuration
Table 7. 10-Lead LFCSP Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic S1 S2 NC GND VDD IN2 IN1 VSS D2 D1 EPAD Description Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. No Connect. Ground (0 V) Reference. Most Positive Power Supply Potential. Logic Control Input. Logic Control Input. Most Negative Power Supply Potential. Drain Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Exposed pad tied to substrate, VSS.
Table 8. 10-Lead MSOP Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic S1 S2 NC GND VDD IN2 IN1 VSS D2 D1 Description Source Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. No Connect. Ground (0 V) Reference. Most Positive Power Supply Potential. Logic Control Input. Logic Control Input. Most Negative Power Supply Potential. Drain Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output.
Table 9. ADG1421/ADG1422 Truth Table
ADG1421 INx 1 0 ADG1422 INx 0 1 Switch Condition On Off
Table 10. ADG1423 Truth Table
ADG1423 INx 0 1 Switch 1 Condition Off On Switch 2 Condition On Off
Rev. 0 | Page 8 of 16
ADG1421/ADG1422/ADG1423 TYPICAL PERFORMANCE CHARACTERISTICS
3.5
4.0
TA = 25C
VDD = +15V VSS = -15V
3.5
3.0
ON RESISTANCE ()
ON RESISTANCE ()
VDD = +10V VSS = -10V 2.5 VDD = +12V VSS = -12V VDD = +13.5V VSS = -13.5V 2.0
3.0 2.5 2.0 1.5 1.0 TA = +125C TA = +85C TA = +25C TA = -40C
1.5 VDD = +15V VSS = -15V 1.0 -16.5 -11.5 -6.5 -1.5 3.5 VS, VD (V) VDD = +16.5V VSS = -16.5V
08487-033
0.5 0 -15
8.5
13.5
-10
-5
0 VS, VD (V)
5
10
15
Figure 6. On Resistance as a Function of VD (VS) for Dual Supply
9
TA = 25C
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply
6
8 7
VDD = 5V VSS = 0V
5
ON RESISTANCE ()
ON RESISTANCE ()
TA= +125C 4 TA= +85C 3 TA= +25C TA= -40C
VDD = 10.8V VSS = 0V
6 5 4 3 2
0 2 4 6 8 VS, VD (V) VDD = 8V VSS = 0V
VDD = 12V VSS = 0V VDD = 13.2V VSS = 0V VDD = 15V VSS = 0V
2
1 VDD= 12V VSS= 0V
10 12 14
08487-032
0
2
4
6 VS, VD (V)
8
10
12
Figure 7. On Resistance as a Function of VD (VS) for Single Supply
5.0
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, +12 V Single Supply
7 VDD = +5V VSS = -5V
TA = 25C
4.5 4.0
VDD = +4.5V VSS = -4.5V
6
ON RESISTANCE ()
ON RESISTANCE ()
3.5 3.0 2.5 2.0 1.5 1.0 0.5
08487-031
5 4
TA = +125C
TA = +85C
VDD = +5V VSS = -5V VDD = +5.5V VSS = -5.5V VDD = +7V VSS = -7V
TA = +25C 3 TA = -40C 2 1
-5
-3
-1
1
3
5
7
-4
-3
-2
-1
0
1
2
3
4
5
VS, VD (V)
VS, VD (V)
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Dual Supply
Rev. 0 | Page 9 of 16
08487-017
0 -7
0 -5
08487-019
0
08487-020
ADG1421/ADG1422/ADG1423
25 VDD = +15V VSS = -15V VBIAS = 10V
90 80 70 IDD PER CHANNEL TA = 25C
20
LEAKAGE CURRENT (nA)
15
IDD (A)
60 50
10
5
ID (OFF) - + IS (OFF) + - IS (OFF) - + ID (OFF) + - ID, IS (ON) + + ID, IS (ON) - -
40 30 20 10 0
VDD = +12V VSS = 0V
VDD = +15V VSS = -15V
0
VDD = +5V VSS = -5V
08487-014
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
TEMPERATURE (C)
LOGIC LEVEL, IN (V)
Figure 12. Leakage Currents as a Function of Temperature, 15 V Dual Supply
25
VDD = 12V VSS = 0V VBIAS = 1V/10V
500
Figure 15. IDD vs. Logic Level
TA = 25C
400 300
20 LEAKAGE CURRENT (nA)
VDD = +5V VSS = -5V VDD = +15V VSS = -15V
CHARGE INJECTION (pC)
15
IS (OFF) + - ID (OFF) - + ID (OFF) + - IS (OFF) - + ID, IS (ON) + + ID, IS (ON) - -
200 100 0 -100 -200 -300
VDD = +12V VSS = 0V
10
5
0
-400
08487-015
0
20
40
60
80
100
120
-10
-5
0
5
10
15
TEMPERATURE (C)
VS (V)
Figure 13. Leakage Currents as a Function of Temperature, +12 V Single Supply
25
Figure 16. Charge Injection vs. Source Voltage
350 300 250
20
LEAKAGE CURRENT (nA)
VDD = +5V VSS = -5V VBIAS = 4.5V
15
TIME (ns)
tOFF (5V)
200 150 100 50 0 -40
10
5
IS (OFF) + - ID (OFF) - + IS (OFF) - + ID (OFF) + - ID, IS (ON) + + ID, IS (ON) - -
tON (5V)
0
tON (+12V) tOFF (+12V) tOFF (15V) tON (15V)
08487-006
-5
08487-016
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
TEMPERATURE( C)
TEMPERATURE (C)
Figure 14. Leakage Currents as a Function of Temperature, 5 V Dual Supply
Figure 17. tTRANSITION Times vs. Temperature
Rev. 0 | Page 10 of 16
08487-034
-5
-500 -15
08487-013
-5
-10
ADG1421/ADG1422/ADG1423
0 TA = 25C VDD = +15V VSS = -15V
0.050 0.045 0.040 0.035 VDD = 5V, VSS = 5V, VS = 5V p-p
-20
OFF ISOLATION (dB)
-40
THD + N (%)
0.030 0.025 0.020 VDD = 15V, VSS = 15V, VS = 10V p-p 0.015 0.010 0.005 RL = 110 TA= 25C 0 5M 10M FREQUENCY (Hz) 15M 20M
08487-011 08487-009
-60
-80
-100
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency
0 -0.5 -1.0 INSERTION LOSS (dB)
-30
08487-008
-120 1k
0
Figure 21. THD + N vs. Frequency
0 -10 -20 NO DECOUPLING CAPACITORS
TA = 25C VDD = +15V VSS = -15V
TA = 25C VDD = +15V VSS = -15V
ACPSRR (dB)
-1.5 -2.0 -2.5 -3.0
-40 -50 -60 -70 -80
DECOUPLING CAPACITORS
-3.5 -4.0 10k
-90
FREQUENCY (Hz)
08487-007
100k
1M
10M
100M
1G
-100
1k
10k
100k FREQUENCY (Hz)
1M
10M
Figure 19. On Response vs. Frequency
Figure 22. ACPSRR vs. Frequency
0
-20
TA = 25C VDD = +15V VSS = -15V
CROSSTALK (dB)
-40
-60
-80
-100
FREQUENCY (Hz)
Figure 20. Crosstalk vs. Frequency
08487-012
-120 10k
100k
1M
10M
100M
1G
Rev. 0 | Page 11 of 16
ADG1421/ADG1422/ADG1423 TEST CIRCUITS
V
ID (ON) NC S D A VD
08487-023
S
D IDS
08487-021
VS
NC = NO CONNECT
Figure 23. On Resistance
IS (OFF) A VS S D ID (OFF) A VD
08487-022
Figure 25. On Leakage
Figure 24. Off Leakage
VDD 0.1F
VSS 0.1F VIN VOUT VIN RL 300 GND CL 35pF VOUT
ADG1421
50%
50%
VDD S VS
VSS D
ADG1422
50% 90%
50% 90%
08487-024
IN
tON
tOFF
Figure 26. Switching Times
VDD 0.1F
VSS 0.1F VIN 0V 50% 50%
VDD VS1 VS2 S1 S2
VSS D1 D2 RL 300 CL 35pF VOUT2 RL 300 CL 35pF VOUT1 VOUT1 0V
90%
90%
VOUT2 0V
90%
90%
IN1, IN2
ADG1423
GND
Figure 27. Break-Before-Make Time Delay
VDD
VSS
VDD RS VS S
VSS D VOUT CL 1nF GND
VIN
ADG1421
ON OFF
IN
VIN VOUT
ADG1422
08487-026
QINJ = CL x VOUT
VOUT
Figure 28. Charge Injection
Rev. 0 | Page 12 of 16
08487-025
tD
tD
ADG1421/ADG1422/ADG1423
VDD 0.1F VSS 0.1F NETWORK ANALYZER
VDD 0.1F VSS 0.1F NETWORK ANALYZER
VDD S IN
VSS
VDD S
VSS
50 D
50 VS VOUT
VIN IN
50 VS D RL 50 VOUT
VIN GND
RL 50
GND
08487-027
OFF ISOLATION = 20 LOG
VS
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 29. Off Isolation
Figure 31. Bandwidth
VDD 0.1F NETWORK ANALYZER VOUT RL 50
VSS 0.1F
VDD VSS 0.1F AUDIO PRECISION
VDD S1
VSS
0.1F
D S2 VS GND
R 50
IN
VDD S
VSS RS
D VIN
08487-028
VS V p-p RL 10k VOUT
08487-030
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
VOUT VS
GND
Figure 30. Channel-to-Channel Crosstalk
Figure 32. THD + N
Rev. 0 | Page 13 of 16
08487-029
VOUT
ADG1421/ADG1422/ADG1423 TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. See Figure 26. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. See Figure 26. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. See Figure 27. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 28. Off Isolation A measure of unwanted signal coupling through an off switch. See Figure 29. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. See Figure 30. Bandwidth The frequency at which the output is attenuated by 3 dB. See Figure 31. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. See Figure 31. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 32. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. See Figure 22.
Rev. 0 | Page 14 of 16
ADG1421/ADG1422/ADG1423 OUTLINE DIMENSIONS
3.10 3.00 2.90
10
6
3.10 3.00 2.90 PIN 1 IDENTIFIER
1
5.15 4.90 4.65
5
0.50 BSC 0.95 0.85 0.75 0.15 0.05 COPLANARITY 0.10 0.30 0.15 15 MAX 1.10 MAX 0.70 0.55 0.40
091709-A
6 0
0.23 0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 33. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
3.00 BSC SQ 0.30 0.23 0.18
6 10 *EXPOSED PAD (BOTTOM VIEW)
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.20)
0.20 REF *FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
031208-B
Figure 34. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1421BRMZ 1 ADG1421BRMZ-REEL71 ADG1421BCPZ-REEL71 ADG1422BRMZ1 ADG1422BRMZ-REEL71 ADG1422BCPZ-REEL71 ADG1423BRMZ1 ADG1423BRMZ-REEL71 ADG1423BCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10- Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10- Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10- Lead Frame Chip Scale Package [LFCSP_WD]
Package Option RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9 RM-10 RM-10 CP-10-9
Branding S2V S2V S2V S2W S2W S2W S2X S2X S2X
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
ADG1421/ADG1422/ADG1423 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08487-0-10/09(0)
Rev. 0 | Page 16 of 16

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